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In each time step (20 ms), two data packets are transmitted between the MLC and LLC, one in each direction. The data integrity is checked on both sides using the cyclic redundancy check. The LLC will acknowledge receiving a correct message from the MLC through a status bit. The MLC will repeat the transmission within a time step, until a correct message from the LLC is received and the slave'LCC
s acknowledge bit is set. Thus, every transmission will be done made at least twice. The MLC signals the end of the (re)transmission phase to the LLC through a separate "chip select" / "slave select" line.

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